1. Field of the Invention
This invention is related to the field of microprocessors, and more particularly, to branch misprediction recovery mechanisms in a microprocessor.
2. Description of the Related Art
Instructions processed in a microprocessor are encoded as a sequence of ones and zeros. For some processor architectures, instructions may be encoded with a fixed length, such as a certain number of bytes. For other architectures, such as the x86 architecture, the length of instructions may vary. The x86 microprocessor architecture specifies a variable length instruction set (i.e., an instruction set in which various instructions are each specified by differing numbers of bytes). For example, the 80386 and later versions of x86 microprocessors employ between 1 and 15 bytes to specify a particular instruction. Instructions have an opcode, which may be 1–2 bytes, and additional bytes may be added to specify addressing modes, operands, and additional details regarding the instruction to be executed.
In some microprocessor architectures, each instruction may be decoded into one or more simpler operations prior to execution. Decoding an instruction may also involve accessing a register renaming map in order to determine the physical register with which each logical register in the instruction is associated and/or to allocate a physical register to store the result of the instruction.
Instructions are fetched into the decode portion of a microprocessor based, in part, on branch predictions made within the processor. In general, the bandwidth of the instruction fetch and decode portions of a microprocessor may determine whether the execution cores can be fully utilized during each execution cycle. However, incorrect branch predictions may degrade the bandwidth of the instruction fetch and decode logic as time and resources are wasted in fetching, decoding, and executing instructions on an incorrectly predicted path.